1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device in which a conductor plug is formed in an opening of an interlevel dielectric layer for interconnecting upper- and lower-level wiring layers in a semiconductor integrated circuit.
2. Description of the Prior Art
A conventional fabrication method of a semiconductor device of this sort is shown in FIGS. 1A and 1B, which is disclosed in the Japanese Non-Examined Patent Publication No. 4-167448 published in June 1992 and 5-275866 published in October 1993.
First, a first interlevel dielectric layer 102 is formed on a semiconductor substructure 101 having active elements therein. The semiconductor substructure 101 typically includes a semiconductor substrate, a patterned insulating layer formed on or over a main surface of the substrate, and a patterned conductive layer formed on the insulating layer.
Next, a metal layer is formed on the first interlevel dielectric layer 102 to be patterned, thereby forming a first wiring layer 103. The first interlevel dielectric layer 102 serves to electrically insulate the first wiring layer 103 from the underlying conductive layer of the substructure 101.
Further, a silicon dioxide (SiO.sub.2) layer serving as a second interlevel dielectric layer 104 is deposited on the first interlevel dielectric layer 102 to cover the first wiring layer 103 by a Plasma-Enhanced Chemical Vapor Deposition (PECVD) process. Then, a contact hole 122 is formed in the second interlevel dielectric layer 104 by popular lithography and etching processes. The contact hole 122 is formed to expose the top of the underlying first wiring layer 103.
Subsequently, a blanket tungsten (W) layer 121 is selectively deposited on the second interlevel dielectric layer 104 to cover the contact hole 122 by a Low-Pressure CVI (LPCVD) process, thereby filling the contact hole 122 with the W layer 121. A part of the W layer 121 is located on the surface of the dielectric layer 104 outside the hole 122. The W layer 121 is contacted with the top of the first wiring layer 103 and the inside wall of the layer 104 within the hole 122.
To planarize the surface of the W layer 121, the excess W layer 121 on the surface of the second interlevel dielectric layer 104 is removed by a Chemical/Mechanical Polishing (CMP) process until the surface of the layer 104 is exposed. At the end of this CMP process, the W layer 122 is selectively left inside the contact hole 122. The state at this stage is shown in FIG. 1A. The remaining W layer within the hole 122 serves as a conductor plug.
The above CMP process for the W layer 121 is performed by the use of a polishing slurry containing abrasive particles such as alumina (Al.sub.2 O.sub.3) particles and an oxidizing agent such as hydrogen peroxide (H.sub.2 O.sub.2). The surface area of the second interlevel dielectric layer 104 also is slightly etched during the CMP process.
Finally, a metal layer is formed on the planarized surfaces of the second interlevel dielectric layer 104 and the W layer 121, and is then patterned, thereby forming a second wiring layer 116. The state at this stage is shown in FIG. 1B. As shown in FIG. 1B, the second wiring layer 116 is contacted with the conductor plug made of the remaining W layer 121 within the contact hole 122.
Thus, the second wiring layer 116 in an upper level is electrically interconnected with the first wiring layer 103 in a lower level through the plug 121, thereby forming a two-level wiring structure over the semiconductor substructure 101.
With the conventional fabrication method shown in FIGS. 1A and 1B, the following problem occurs.
Specifically, as shown in FIG. 1A, a void 123 tends to be formed within the contact hole 122 at the end of the CMP process and/or the thickness of the remaining W layer 121 within the hole 122 tends to be decreased. The void 123 is caused by the fact that the W layer 121 has a depression at a corresponding position to the contact hole 122 according to the configuration of the hole 122. Since the polishing slurry contains the oxidizing agent for the W layer 121, the W layer 122 tends to be readily etched in the vicinity of the depression during the CHP process, resulting in the void 123 within the contact hole 122, as shown in FIG. 1A.
Also, when the W layer 121 has the void 123 within the contact hole 122, the W layer 122 is readily etched vertically and laterally by the oxidizing agent in the vicinity of the void 123. Thus, the thickness of the W layer 121 inside the hole 122 decreases during the CMP process.
Further, the above problem relating to the void 123 causes another problem that the fabrication yield and reliability of a semiconductor integrated circuit fabricated by the above conventional method is remarkably degraded.